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| ICX069AL Diagonal 4.5mm (Type 1/4) CCD Image Sensor for CCIR B/W Video Cameras Description The ICX069AL is an interline CCD solid-state image sensor suitable for CCIR black-and-white video cameras. High sensitivity and low dark current are achieved through the adoption of HAD (HoleAccumulation Diode) sensors. This chip features a field period readout system and an electronic shutter with variable charge-storage time. The package is a 10mm-square 14-pin DIP (Plastic). Features * High resolution, high sensitivity and low dark current * Horizontal register: 3.6 to 5.0V drive * No voltage adjustment (Reset gate and substrate bias are not adjusted.) * Low smear * Continuous variable-speed shutter Device Structure * Interline CCD image sensor * Image size: * Number of effective pixels: * Total number of pixels: * Chip size: * Unit cell size: * Optical black: * Number of dummy bits: * Substrate material: 14 pin DIP (Plastic) Pin 1 2 V 12 3 Pin 8 H 40 Optical black position (Top View) Diagonal 4.5mm (Type 1/4) 752 (H) x 582 (V) approx. 440K pixels 795 (H) x 596 (V) approx. 470K pixels 4.47mm (H) x 3.80mm (V) 4.85m (H) x 4.65m (V) Horizontal (H) direction: Front 3 pixels, rear 40 pixels Vertical (V) direction: Front 12 pixels, rear 2 pixels Horizontal 22 Vertical 1 (even fields only) Silicon Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits. -1- E96503D99 ICX069AL VOUT GND V1 V2 7 6 5 4 V3 NC 3 2 Vertical Register Note) Horizontal Register Note) 8 9 10 11 12 13 14 : Photo sensor GND VL VDD Pin Description Pin No. 1 2 3 4 5 6 7 Symbol V4 V3 V2 V1 NC GND VOUT GND Signal output Description Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock Vertical register transfer clock SUB Pin No. 8 9 10 11 12 13 14 H1 H2 RG V4 1 Block Diagram and Pin Configuration (Top View) Symbol VDD GND SUB VL RG H1 H2 Description Supply voltage GND Substrate clock Protective transistor bias Reset gate clock Horizontal register transfer clock Horizontal register transfer clock Absolute Maximum Ratings Item Substrate clock SUB - GND VDD, VOUT - GND Supply voltage VDD, VOUT - SUB V1, V2, V3, V4 - GND Clock input voltage V1, V2, V3, V4 - SUB Ratings -0.3 to +40 -0.3 to +18 -30 to +9 -15 to +16 to +10 to +15 to +16 -16 to +16 -10 to +15 -55 to +10 -65 to +0.3 -0.3 to +27.5 -0.3 to +20.5 -0.3 to +17.5 -30 to +80 -10 to +60 Unit V V V V V V V V V V V V V V C C 1 Remarks Voltage difference between vertical clock input pins Voltage difference between horizontal clock input pins H1, H2 - V4 H1, H2 - GND H1, H2 - SUB VL - SUB V1, V3, VDD, VOUT - VL RG - GND V2, V4, H1, H2, GND - VL Storage temperature Operating temperature 1 +24V (Max.) when clock width < 10s, clock duty factor < 0.1%. -2- ICX069AL Bias Conditions Item Supply voltage Protective transistor bias Substrate clock Symbol VDD VL SUB Min. 14.55 Typ. 15.0 1 2 Max. 15.45 Unit V Remarks 1 VL setting is the VVL voltage of the vertical transfer clock waveform, or the same power supply as the VL power supply for the V driver should be used. 2 Do not apply a DC bias to the substrate clock pin, because a DC bias is generated within the CCD. DC Characteristics Item Supply current Symbol IDD Min. Typ. 6 Max. 8 Unit mA Remarks Clock Voltage Conditions Item Readout clock voltage Symbol VVT VVH1, VVH2 VVH3, VVH4 VVL1, VVL2, VVL3, VVL4 VV Vertical transfer clock voltage VVH3 - VVH VVH4 - VVH VVHH VVHL VVLH VVLL Horizontal transfer clock voltage VH VHL VRG Reset gate clock voltage VRGLH - VRGLL VRGH Substrate clock voltage VSUB 3.3 -0.05 4.5 5.0 0 5.0 Min. 14.55 -0.05 -0.2 -8.0 6.8 -0.25 -0.25 Typ. 15.0 0 0 -7.5 7.5 Max. 15.45 0.05 0.05 -7.0 8.05 0.1 0.1 0.3 0.3 0.3 0.3 5.25 0.05 5.5 0.8 VDD + VDD + VDD + 0.3 0.6 0.9 21.5 22.5 23.5 Unit V V V V V V V V V V V V V V V V V Waveform diagram 1 2 2 2 2 2 2 2 2 2 2 3 3 4 4 4 5 Input through 0.01F capacitance Low-level coupling High-level coupling High-level coupling Low-level coupling Low-level coupling VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) VVH = (VVH1 + VVH2)/2 Remarks -3- ICX069AL Clock Equivalent Circuit Constant Item Capacitance between vertical transfer clock and GND Symbol CV1, CV3 CV2, CV4 CV12, CV34 Capacitance between vertical transfer clocks CV23, CV41 CV13 CV24 Capacitance between horizontal transfer clock and GND Capacitance between horizontal transfer clocks Capacitance between reset gate clock and GND Capacitance between substrate clock and GND Vertical transfer clock series resistor Vertical transfer clock ground resistor Horizontal transfer clock series resistor Reset gate clock series resistor CH1, CH2 CHH CRG CSUB R1, R2, R3, R4 RGND RH RRG Min. Typ. 680 470 220 220 75 75 33 30 5 170 82 15 39 39 Max. Unit pF pF pF pF pF pF pF pF pF pF Remarks V1 CV12 V2 R1 R2 RH H1 RH H2 CHH CV23 CV13 CH1 CH2 CV1 CV41 CV24 CV4 R4 RGND CV34 CV2 CV3 R3 V4 V3 Vertical transfer clock equivalent circuit Horizontal transfer clock equivalent circuit RRG RG CRG Reset gate clock equivalent circuit -4- ICX069AL Drive Clock Waveform Conditions (1) Readout clock waveform 100% 90% II II M VVT 10% 0% tr twh tf 0V M 2 (2) Vertical transfer clock waveform V1 V3 VVH1 VVHH VVH VVHL VVHH VVHH VVHL VVHL VVH3 VVHH VVHL VVH VVL1 VVLH VVL3 VVLL VVL VVLH VVL VVLL V2 VVHH VVHH V4 VVHH VVHH VVH VVHL VVH VVH2 VVHL VVHL VVH4 VVHL VVL2 VVLH VVLH VVLL VVL VVL4 VVLL VVL VVH = (VVH1 + VVH2)/2 VVL = (VVL3 + VVL4)/2 VV = VVHn - VVLn (n = 1 to 4) -5- ICX069AL (3) Horizontal transfer clock waveform tr twh tf 90% VH 10% VHL twl (4) Reset gate clock waveform tr twh tf VRGH twl Point A RG waveform VRGLH VRGL VRGLL VRG VRGL + 0.5V H1 waveform 2.5V VRGLH is the maximum value and VRGLL is the minimum value of the coupling waveform during the period from Point A in the above diagram until the rising edge of RG. In addition, VRGL is the average value of VRGLH and VRGLL. VRGL = (VRGLH + VRGLL)/2 Assuming VRGH is the minimum value during the interval twh, then: VRG = VRGH - VRGL (5) Substrate clock waveform 100% 90% M VSUB 10% VSUB 0% (A bias generated within the CCD) M 2 tf tr twh -6- ICX069AL Clock Switching Characteristics Item Readout clock Vertical transfer clock Horizontal transfer clock During imaging Symbol VT V1, V2, V3, V4 H1 H2 19 21 24 26 5.38 5.38 11 13 51 21 19 26 24 10 10 0.01 0.01 3 0.5 15 15 twh twl tr tf Unit Remarks s During readout Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. Min. Typ. Max. 2.3 2.5 0.5 15 10 10 0.01 0.01 3 0.5 0.5 250 ns 1 15 15 ns 2 During H1 parallel-serial H2 conversion RG SUB s ns s During drain charge Reset gate clock Substrate clock 1.5 1.8 1 When vertical transfer clock driver CXD1267AN is used. 2 tf tr - 2ns, and the cross-point voltage (VCR) for the H1 rising side of the H1 and H2 waveforms must be at least VH/2 [V]. Item Horizontal transfer clock Symbol H1, H2 two Min. 16 Typ. 20 Max. Unit ns Remarks 3 3 The overlap period for twh and twl of horizontal transfer clocks H1 and H2 is two. -7- ICX069AL Image Sensor Characteristics Item Sensitivity Saturation signal Smear Video signal shading Dark signal Dark signal shading Flicker Lag Symbol S Vsat Sm SH Vdt Vdt F Lag Min. 220 540 0.009 0.015 20 25 2 1 2 0.5 Typ. 280 Max. Unit mV mV % % % mV mV % % Measurement method 1 2 3 4 4 5 6 7 8 (Ta = 25C) Remarks Ta = 60C Zone 0 and I Zone 0 to II' Ta = 60C Ta = 60C Zone Definition of Video Signal Shading 752 (H) 12 12 8 H 8 V 10 H 8 582 (V) Zone 0, I Zone II, II' V 10 6 Ignored region Effective pixel region -8- ICX069AL Image Sensor Characteristics Measurement Method Measurement conditions 1) In the following measurements, the device drive conditions are at the typical values of the bias and clock voltage conditions. 2) In the following measurements, spot blemishes are excluded and, unless otherwise specified, the optical black (OB) level is used as the reference for the signal output, and the value measured at point [A] in the drive circuit example is used. Definition of standard imaging conditions 1) Standard imaging condition I: Use a pattern box (luminance: 706cd/m2, color temperature of 3200K halogen source) as a subject. (Pattern for evaluation is not applicable.) Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter and image at F8. The luminous intensity to the sensor receiving surface at this point is defined as the standard sensitivity testing luminous intensity. 2) Standard imaging condition II: Image a light source (color temperature of 3200K) with a uniformity of brightness within 2% at all angles. Use a testing standard lens with CM500S (t = 1.0mm) as an IR cut filter. The luminous intensity is adjusted to the value indicated in each testing item by the lens diaphragm. 1. Sensitivity Set to standard imaging condition I. After selecting the electronic shutter mode with a shutter speed of 1/250s, measure the signal output (Vs) at the center of the screen and substitute the value into the following formula. S = Vs x 250 50 [mV] 2. Saturation signal Set to standard imaging condition II. After adjusting the luminous intensity to 10 times the intensity with the average value of the signal output, 200mV, measure the minimum value of the signal output. 3. Smear Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity to 500 times the intensity with the average value of the signal output, 200mV. When the readout clock is stopped and the charge drain is executed by the electronic shutter at the respective H blankings, measure the maximum value (VSm [mV]) of the signal output and substitute the value into the following formula. Sm = 1 VSm 1 x x x 100 [%] (1/10V method conversion value) 10 200 500 4. Video signal shading Set to standard imaging condition II. With the lens diaphragm at F5.6 to F8, adjust the luminous intensity so that the average value of the signal output is 200mV. Then measure the maximum (Vmax [mV]) and minimum (Vmin [mV]) values of the signal output and substitute the values into the following formula. SH = (Vmax - Vmin)/200 x 100 [%] -9- ICX069AL 5. Dark signal Measure the average value of the signal output (Vdt [mV]) with the device ambient temperature 60C and the device in the light-obstructed state, using the horizontal idle transfer level as a reference. 6. Dark signal shading After measuring 5, measure the maximum (Vdmax [mV]) and minimum (Vdmin [mV]) values of the dark signal output and substitute the values into the following formula. Vdt = Vdmax - Vdmin [mV] 7. Flicker Set to standard imaging condition II. Adjust the luminous intensity so that the average value of the signal output is 200mV, and then measure the difference in the signal level between fields (Vf [mV]). Then substitute the value into the following formula. F = (Vf/200) x 100 [%] 8. Lag Adjust the signal output value generated by strobe light to 200mV. After setting the strobe light so that it strobes with the following timing, measure the residual signal (Vlag). Substitute the value into the following formula. Lag = (Vlag/200) x 100 [%] FLD V1 Light Strobe light timing Signal output 200mV Output Vlag (lag) - 10 - Drive Circuit 15V 20 100k 19 18 17 16 1/35 V 3.3/16V 22/16V 15 14 13 12 11 0.1 -7.5V 1 2 3 XSUB 4 XV2 5 XV1 6 CXD1267AN XSG1 7 XV3 8 XSG2 9 10 XV4 22/20V 1 2 3 4 5 6 7 100 V4 V3 V2 V1 NC GND VOUT RG H1 VL H2 14 13 12 11 10 SUB 9 GND 8 2200p 0.01 3.3/20V 1M H2 H1 100k 1/20V 0.01 RG VDD - 11 - ICX069 (BOTTOM VIEW) [A] CCD OUT 3.9k 2SK523 ICX069AL ICX069AL Spectral Sensitivity Characteristics (excludes both lens characteristics and light source characteristics) 1.0 0.9 0.8 0.7 Relative Response 0.6 0.5 0.4 0.3 0.2 0.1 0.0 400 500 600 700 Wave Length [nm] 800 900 1000 Sensor Readout Clock Timing Chart V1 V2 Odd Field V3 V4 33.6 0.2 V1 V2 Even Field V3 V4 1.5 2.6 2.6 2.6 2.6 unit : s - 12 - Drive Timing Chart (Vertical Sync) FLD VD BLK HD 10 15 20 25 320 325 620 625 1 2 3 4 5 310 315 330 335 - 13 - 24 6 135 246 135 582 581 V1 V2 V3 V4 CCD OUT 581 582 135 24 6 135 246 340 ICX069AL Drive Timing Chart (Horizontal Sync) HD BLK H1 1 2 3 5 10 10 40 20 22 1 2 3 1 2 3 20 H2 10 745 RG V1 - 14 - V2 V3 V4 SUB 750 752 1 3 5 20 30 ICX069AL ICX069AL Notes on Handling 1) Static charge prevention CCD image sensors are easily damaged by static discharge. Before handling be sure to take the following protective measures. a) Either handle bare handed or use non-chargeable gloves, clothes or material. Also use conductive shoes. b) When handling directly use an earth band. c) Install a conductive mat on the floor or working table to prevent the generation of static electricity. d) Ionized air is recommended for discharge when handling CCD image sensor. e) For the shipment of mounted substrates, use boxes treated for the prevention of static charges. 2) Soldering a) Make sure the package temperature does not exceed 80C. b) Solder dipping in a mounting furnace causes damage to the glass and other defects. Use a ground 30W soldering iron and solder each pin in less than 2 seconds. For repairs and remount, cool sufficiently. c) To dismount an image sensor, do not use a solder suction equipment. When using an electric desoldering tool, use a thermal controller of the zero cross On/Off type and connect it to ground. 3) Dust and dirt protection Image sensors are packed and delivered by taking care of protecting its glass plates from harmful dust and dirt. Clean glass plates with the following operation as required, and use them. a) Perform all assembly operations in a clean room (class 1000 or less). b) Do not either touch glass plates by hand or have any object come in contact with glass surfaces. Should dirt stick to a glass surface, blow it off with an air blower. (For dirt stuck through static electricity ionized air is recommended.) c) Clean with a cotton bud and ethyl alcohol if the grease stained. Be careful not to scratch the glass. d) Keep in a case to protect from dust and dirt. To prevent dew condensation, preheat or precool when moving to a room with great temperature differences. e) When a protective tape is applied before shipping, just before use remove the tape applied for electrostatic protection. Do not reuse the tape. 4) Installing (attaching) a) Remain within the following limits when applying a static load to the package. Do not apply any load more than 0.7mm inside the outer perimeter of the glass portion, and do not apply any load or impact to limited portions. (This may cause cracks in the package.) Cover glass 50N Plastic package Compressive strength 50N 1.2Nm Torsional strength b) If a load is applied to the entire surface by a hard component, bending stress may be generated and the package may fracture, etc., depending on the flatness of the bottom of the package. Therefore, for installation, use either an elastic load, such as a spring plate, or an adhesive. - 15 - ICX069AL c) The adhesive may cause the marking on the rear surface to disappear, especially in case the regulated voltage value is indicated on the rear surface. Therefore, the adhesive should not be applied to this area, and indicated values should be transferred to the other locations as a precaution. d) The notch of the package is used for directional index, and that can not be used for reference of fixing. In addition, the cover glass and seal resin may overlap with the notch of the package. e) If the lead bend repeatedly and the metal, etc., clash or rub against the package, the dust may be generated by the fragments of resin. f) Acrylate anaerobic adhesives are generally used to attach CCD image sensors. In addition, cyanoacrylate instantaneous adhesives are sometimes used jointly with acrylate anaerobic adhesives. (reference) 5) Others a) Do not expose to strong light (sun rays) for long periods. For continuous using under cruel condition exceeding the normal using condition, consult our company. b) Exposure to high temperature or humidity will affect the characteristics. Accordingly avoid storage or usage in such conditions. c) The brown stain may be seen on the bottom or side of the package. But this does not affect the CCD characteristics. d) This package has 2 kinds of internal structure. However, their package outline, optical size, and strength are the same. Structure A Package Chip Metal plate (lead frame) Structure B Cross section of lead frame The cross section of lead frame can be seen on the side of the package for structure A. - 16 - Package Outline Unit: mm 14 pin DIP (400mil) A 0 to 9 5.0 8 D C 8 14 14 ~ 10.16 7.0 ~ 2.5 5.0 V 7 7 1 H 0.5 B' 1. "A" is the center of the effective image area. 1.0 3.35 0.15 7.0 2.5 2.6 1.27 3.5 0.3 - 17 - 2. The two points "B" of the package are the horizontal reference. The point "B'" of the package is the vertical reference. 3. The bottom "C" of the package, and the top of the cover glass "D" are the height reference. 4. The center of the effective image area relative to "B" and "B'" is (H, V) = (5.0, 5.0) 0.15mm. 5. The rotation angle of the effective image area relative to H and V is 1. ~ 1.27 M 0.3 0.46 6. The height from the bottom "C" to the effective image area is 1.41 0.10mm. The height from the top of the cover glass "D" to the effective image area is 1.94 0.15mm. 7. The tilt of the effective image area relative to the bottom "C" is less than 25m. The tilt of the effective image area relative to the top "D" of the cover glass is less than 25m. 8. The thickness of the cover glass is 0.75mm, and the refractive index is 1.5. 9. The notch of the package is used only for directional index, that must not be used for reference of fixing. 0.3 PACKAGE STRUCTURE PACKAGE MATERIAL Plastic LEAD TREATMENT GOLD PLATING LEAD MATERIAL 42 ALLOY PACKAGE WEIGHT 0.6g 0.25 1.0 1 8.9 10.0 0.1 8.9 10.0 0.1 1.7 B 1.7 2.5 ICX069AL |
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